1. Field of the Invention.
The present invention relates to integrated circuits, and more particularly, to such circuits employing metal oxide semiconductor (MOS) technology.
2. Description of Related Art.
Monolithic complementary metal oxide semiconductor (CMOS) integrated circuits have transistors of both carrier types, that is, P-channel and N-channel transistors. One such transistor carrier type may be formed directly into the substrate of the device. For example, if the substrate has been doped to an N conductivity type, P-channel transistors may be formed directly into the substrate. However, the transistors of the opposite carrier type, N-channel transistors, are typically formed in P-type wells formed within the N-type substrate.
One problem inherent with CMOS integrated circuits of this nature is that an N+ diffusion region in a P well can create a parasitic vertical NPN bipolar transistor. Similarly, a P+ diffusion region adjacent a P- well can form a parasitic lateral PNP bipolar transistor. Accordingly, the substrate of the device could function as a common base for each of the PNP parasitic devices, and could also function as a common collector for the NPN parasitic transistors.
Under certain circumstances, the base-emitter junction of the PNP transistor may become forward biased, activating not only the PNP transistor but also a nearby NPN parasitic transistor. Two such activated transistors can function as a silicon controlled rectifier (SCR) such that even after the condition which initially caused the forward biasing of the base-emitter junction of the PNP transistor disappears, the SCR can remain turned on. This condition is often referred to as "latch-up" and can cause an undesirable high current to be drawn from the device power supply which can cause destruction of the device.
Previous attempts to prevent latch-up have been directed primarily at reducing the resistance of certain current paths through the metallization lines, substrates or wells, as appropriate. In addition, the gain of the lateral and vertical parasitic bipolar transistors can also be reduced by various processing techniques to reduce the likelihood of inadvertent activation of an SCR structure. For example, guard rings can reduce the number of minority carriers in the substrate to thereby reduce the effective gain (.beta.) of the parasitic lateral transistor. However, where significant transient currents may be present in the device, these prior techniques have often been found to be either insufficient or inconvenient to apply in various applications.